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ADVANCE INFORMATION
PE9704
Product Description
Peregrine's PE9704 is a high-performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space PLLs. The PE9704 features a /10/11 dual modulus prescaler, counters, and a phase comparator as shown in Figure 1. Counter values are programmable through a serial interface, and can also be directly hard wired. The PE9704 is optimized for commercial space applications. Single Event Latch-up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. Fabricated in Peregrine's patented UTSi(R) (Ultra Thin Silicon) CMOS technology, the PE9704 offers excellent RF performance and intrinsic radiation tolerance.
3.0 GHz Integer-N PLL for Rad Hard Applications
Features * 3.0 GHz operation * /10/11 dual modulus prescaler * Phase detector output * Serial interface or hardwired programmable * Ultra-low phase noise * SEU < 10-9 errors / bit-day * 100 Krad (Si) total dose * 44-lead CQFJ
Figure 1. Block Diagram
Prescaler 10 / 11
MSEL
FIN
Main Counter 13
Serial Control
3
20-Bit Frequency Register
fp 20 19* fc
Phase Detector
PD_U PD_D
M(8:0) Direct A(3:0) Control R(5:0) FR
LD 6 6 C ext
R Counter * prescaler bypass not available in Direct mode
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PE9704
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Figure 2. Pin Configuration
GND GND GND ENH VDD LD R3 R2 R1 R0 FR
6
R4 R5 M0 M1 VDD VDD M2 M3 S_WR, M4 DATA, M5 GND
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CEXT VDD PD_U PD_D GND N/C VDD DOUT VDD N/C GND
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CLOCK, M6 DMODE M7 M8 A0 E_WR, A1 A2 A3 VDD FIN GND
Table 1. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Name
VDD R0 R1 R2 R3 GND R4 R5 M0 M1 VDD VDD M2 M3 S_WR M4
Interface Mode
Both Direct Direct Direct Direct Both Direct Direct Direct Direct Both Both Direct Direct Serial Direct Serial
Type
(Note 1) Input Input Input Input (Note 1) Input Input Input Input (Note 1) (Note 1) Input Input Input Input Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. R Counter bit0 R Counter bit1 R Counter bit2 R Counter bit3 Ground R Counter bit4 R Counter bit5 (MSB) M Counter bit0 M Counter bit1 Same as pin 1 Same as pin 1 M Counter bit2 M Counter bit3 Frequency register load enable input. Buffered data is transferred to the frequency register on S_WR rising edge. M Counter bit4 Binary serial data input. Data is entered LSB first, and is clocked serially into the 20bit frequency control register (E_WR "low") or the 8-bit enhancement register (E_WR "high") on the rising edge of CLOCK.
15
16
DATA
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0083~00B
| | UTSi CMOS RFIC SOLUTIONS
Page 2 of 12
PE9704
Advance Information
Pin No.
Pin Name
M5
Interface Mode
Direct Both Serial Direct Direct Direct Direct Both Both Serial Direct Direct Direct Both Both Both
Type
Input M Counter bit5 Ground Input Input Input Input Input Input (Note 1) Input Input Input Input Input
Description
17
GND CLOCK M6
18
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR "low") or the 8-bit enhancement register (E_WR "high") on the rising edge of CLOCK. M Counter bit6 M Counter bit7 M Counter bit8 (MSB) A Counter bit0 Selects direct interface mode (DMODE=1) or serial interface mode (DMODE=0) Same as pin 1 Enhancement register write enable. While E_WR is "high", DATA can be serially clocked into the enhancement register on the rising edge of CLOCK. A Counter bit1. A Counter bit2 A Counter bit3 (MSB) RF prescaler input from the VCO. 3.0 GHz maximum frequency. Ground. Ground. No connect.
19 20 21 22 23
M7 M8 A0 DMODE VDD E_WR A1
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Note 1: Note 2:
A2 A3 FIN GND GND N/C VDD DOUT VDD N/C GND PD_D PD_U VDD CEXT GND GND FR ENH LD
Both Serial Both
(Note 1) Output (Note 1)
Same as pin 1 Data Out. The Main Counter output, R Counter output, or dual modulus prescaler select (MSEL) can be routed to DOUT through enhancement register programming. Same as pin 1 No connect.
Both Both Both Both Both Both Both Both Both Serial Input Output, OD Output (Note 1) Output Output
Ground. PD_D pulses down when fp leads fc. PD_U pulses down when fc leads fp. Same as pin 1 Logical "NAND" of PD_U and PD_D, passed through an on-chip, 2 k series resistor. Connecting CEXT to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. Ground Ground Reference frequency input Enhancement mode. When asserted low ("0"), enhancement register bits are functional. Lock detect output, the open-drain logical inversion of CEXT. When the loop is locked, LD is high impedance; otherwise LD is a logic low ("0").
VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. All digital input pins have 70 k pull-down resistors to ground.
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PE9704
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Table 2. Absolute Maximum Ratings
Symbol
VDD VI II IO Tstg
Electrostatic Discharge (ESD) Precautions
Units
V V mA mA C 4.0
Parameter/Conditions
Supply voltage Voltage on any input DC into any input DC into any output Storage temperature range
Min
-0.3 -0.3 -10 -10 -65
Max
VDD + 0.3 +10 +10 150
When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
VDD TA
Parameter/Conditions
Supply voltage Operating ambient temperature range
Min
2.85 -40
Max
3.15 85
Units
V C
Table 4. ESD Ratings
Symbol
VESD
Parameter/Conditions
ESD voltage (Human Body Model) - Note 1
Level
1000
Units
V
Note 1:
Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0083~00B
| | UTSi CMOS RFIC SOLUTIONS
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Table 5. DC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
IDD
Parameter
Operational supply current; Prescaler disabled Prescaler enabled High level input voltage Low level input voltage High level input current Low level input current High level input current Low level input current Output voltage LOW Output voltage HIGH Output voltage LOW, CEXT Output voltage HIGH, CEXT Output voltage LOW, LD
Conditions
VDD = 2.85 to 3.15 V
Min
Typ
10 24
Max
Units
mA mA V
31
Digital Inputs: All except FR, FIN (all digital inputs have 70k ohm pull-up resistors) VIH VIL IIH IIL IIHR IILR VOLD VOHD VOLC VOHC VOLLD VDD = 2.85 to 3.15 V VDD = 2.85 to 3.15 V VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V Iout = 6 mA Iout = -3 mA Iout = 100 Iout = -100 Iout = 6 mA VDD - 0.4 0.4 VDD - 0.4 0.4 -100 0.4 -1 +100 0.7 x VDD 0.3 x VDD +70 V A A A A V V V V V
Reference Divider input: FR
Counter and phase detector outputs: fc, fp.
Lock detect outputs: CEXT, LD
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PE9704
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Table 6. AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
fClk tClkH tClkL tDSU tDHLD tPW tCWR tCE tWRC tEC tMDO FIN PFin FIN PFin Reference Divider FR PFr Phase Detector fc Note 1: Comparison frequency (Note 3) 20 MHz Operating frequency Reference input power (Note 2) (Note 3) Single-ended input -2 100 MHz dBm
Parameter
CLOCK Serial data clock frequency CLOCK Serial clock HIGH time CLOCK Serial clock LOW time DATA set-up time after CLOCK rising edge DATA hold time after CLOCK rising edge S_WR pulse width CLOCK rising edge to S_WR rising edge. CLOCK falling edge to E_WR transition S_WR falling edge to CLOCK rising edge. E_WR transition to CLOCK rising edge MSEL data out delay after FIN rising edge Operating frequency Input level range Operating frequency Input level range
Conditions
(Note 1)
Min
Max
10
Units
MHz ns ns ns ns ns ns ns ns ns
Control Interface and Latches (see Figures 1and 3) 30 30 10 10 30 30 30 30 30 CL = 12 pf 500 External AC coupling -5 50 External AC coupling -5 8 3000 5 300 5
ns MHz dBm MHz dBm
Main Divider (Including Prescaler)
Main Divider (Prescaler Bypassed)
Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk specification.
Note 2: Note 3:
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Parameter is guaranteed through characterization only and is not tested.
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0083~00B
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PE9704
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Functional Description The PE9704 consists of a prescaler, counters, a phase detector, and control logic. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters "R" and "M" divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter ("A") is used in the modulus select logic. The phase-frequency detector generates up and down frequency control signals. The control logic includes a selectable chip interface. Data can be written via a serial bus or hardwired directly to the pins. There are also various operational and test modes and a lock detect output. Main Counter Chain Normal Operating Mode Setting the PB control bit "low" enables the /10/11 prescaler. The main counter chain then divides the RF input frequency (FIN) by an integer derived from the values in the "M" and "A" counters. In this mode, the output from the main counter chain (fp) is related to the VCO frequency (FIN) by the following equation:
fp = FIN / [10 x (M + 1) + A] where A M + 1, 1 M 511 (1)
Prescaler Bypass Mode Setting the frequency control register bit PB "high" allows FIN to bypass the /10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. This mode is only available when using the serial port to set the frequency control bits. The following equation relates FIN to the reference frequency FR:
FIN = (M + 1) x (FR / (R+1)) ) where 1 M 511 (3)
Reference Counter The reference counter chain divides the reference frequency FR down to the phase detector comparison frequency fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation:
fc = FR / (R + 1) where 0 R 63 (4)
Note that programming R with "0" will pass the reference frequency (FR) directly to the phase detector.
When the loop is locked, FIN is related to the reference frequency (FR) by the following equation:
FIN = [10 x (M + 1) + A] x (FR / (R+1)) where A M + 1, 1 M 511 (2)
A consequence of the upper limit on A is that FIN must be greater than or equal to 90 x (FR / (R+1)) to obtain contiguous channels. The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of "1" will result in a minimum M counter divide ratio of "2".
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Register Programming Serial Interface Mode Serial Interface Mode is selected by setting the DMODE input "low". While the E_WR input is "low", serial data (DATA input), B0 to B19, is clocked into a buffer register on the rising edge of CLOCK, LSB (B0) first. The contents from this buffer register are transferred into the frequency control register on the rising edge of S_WR according to the timing diagram shown in Figure 3. This data controls the counters as shown in Table 7. While the E_WR input is "high", serial data (DATA input), B0 to B7, is clocked into a buffer register on the rising edge of CLOCK, LSB (B0) first. The
contents from this buffer register are transferred into the enhancement register on the falling edge of E_WR according to the timing diagram shown in Figure 3. After the falling edge of E_WR, the data provides control bits as shown in Table 8. These bits are active when the Enh input is "low". Direct Interface Mode Direct Interface Mode is selected by setting the DMODE input "high". In this mode, the counter values are set directly at external pins as shown in Table 7 and Figure 2. All frequency control register bits are addressable except PB (it is not possible to bypass the /10/11 dual modulus prescaler in Direct Mode).
Table 7. Frequency Register Programming
Interface Mode Serial* Direct Enh 1 1 DMODE 0 1 R5 B0 R5 R4 B1 R4 M8 B2 M8 M7 B3 M7 PB B4 0 M6 B5 M6 M5 B6 M5 M4 B7 M4 M3 B8 M3 M2 B9 M2 M1 B10 M1 M0 B11 M0 R3 B12 R3 R2 B13 R2 R1 B14 R1 R0 B15 R0 A3 B16 A3 A2 B17 A2 A1 B18 A1 A0 B19 A0
* Data is clocked serially on CLOCK rising edge while E_WR is "low" and transferred to frequency register on S_WR rising edge.
LSB (first in)
MSB (last in)
Table 8. Enhancement Register Programming
Interface Mode Serial** Enh 0 DMODE X Reserved* B0 Reserved* B1 fp output B2 Power down B3 Counter load B4 MSEL output B5 fc output B6 Reserved* B7
* Program to 0 * Data is clocked serially on CLOCK rising edge while E_WR is "low" and transferred to frequency register on S_WR rising edge.
LSB (first in)
MSB (last in)
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0083~00B
| | UTSi CMOS RFIC SOLUTIONS
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PE9704
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Figure 3. Serial Interface Mode Timing Diagram
DATA
E_WR
tEC tCE
CLOCK
S_WR
tDSU tDHLD tClkH tClkL tCWR tPW tWRC
Enhancement Register The functions of the enhancement register bits are shown below. All bits are active high. Operation is undefined if more than one output is sent to DOUT. Table 9. Enhancement Register Bit Functionality
Bit Function
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Reserved** Reserved** fp output Power down Counter load MSEL output fc output Reserved** Drives the M counter output onto the DOUT output. Power down of all functions except programming interface. Immediate and continuous load of counter programming. Drives the internal dual modulus prescaler modulus select (MSEL) onto the DOUT output. Drives the R counter output onto the DOUT output
Description
** Program to 0
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Phase Detector Outputs The phase detector is triggered by rising edges from the main counter (fp) and the reference counter (fc). It has two outputs, PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses "low". If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses "low". The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is 430 mV / radian. PD_U and PD_D are designed to drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency and PD_D results in a decrease in VCO frequency. Software tools for designing the active loop filter can be found at Peregrine's web site (www.peregrine-semi.com).
Lock Detect Output A lock detect signal is provided at pin LD, via the pin CEXT (see Figure 1). CEXT is the logical "NAND" of PD_U and PD_D waveforms, driven through a series 2k ohm resistor. Connecting CEXT to an external shunt capacitor provides integration of this signal. The CEXT signal is then sent to the LD pin through an internal inverting comparator with an open drain output. Thus LD is an "AND" function of PD_U and PD_D.
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0083~00B
| | UTSi CMOS RFIC SOLUTIONS
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PE9704
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Figure 4. Package Drawing
44-lead CQFJ
All dimensions are in mils
Table 10. Ordering Information
Order Code
9704-01 9704-11 9704-00
Part Marking
PE9704 ES PE9704 PE9704 EK
Description
Engineering Samples Flight Units Evaluation Kit
Package
44-pin CQFJ 44-pin CQFJ
Shipping Method
40 units / Tray 40 units / Tray 1 / Box
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